Power control circuit

ABSTRACT

A power control circuit includes a negative feedback loop, and a radio frequency signal path including a first NMOS transistor having a gate configured as a radio frequency signal input end, a drain connected with a source of a second NMOS transistor, and a source connected with a ground terminal. A drain of the second NMOS transistor is configured as a radio frequency signal output end and connected with a first voltage source. The negative feedback loop includes a third NMOS transistor having a gate connected with an output end of a differential amplifier, a source connected with the ground terminal, and a drain connected with a source of a fourth NMOS transistor having a gate connected with a reverse input end of the differential amplifier and with a second voltage source, and a drain connected with a forward input end and a first bias current source.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of International Application No.PCT/CN2020/118564 filed on Sep. 28, 2020, which claims priority toChinese Patent Application No. 202010099884.6 filed on Feb. 18, 2020.The disclosures of these applications are hereby incorporated byreference in their entirety.

BACKGROUND

Radio-frequency power amplifiers may also be referred to as poweramplifiers. When a power amplifier is saturated, a power control circuitis required to control the output power of the power amplifier. Thereare generally two ways of power control, namely current control andvoltage control, respectively. Herein, the way of current control is tocontrol the gate bias voltage of the amplification transistor of thepower amplifier so as to control the bias current of the amplificationtransistor.

SUMMARY

When a power control circuit is configured to control the output powerof the radio frequency power amplifier, a channel length modulationeffect may affect or reduce the performance of the radio frequencyamplifier, and various embodiments of the present disclosure provide apower control circuit that can address such effects.

Some embodiments of the disclosure provide a power control circuit,including: a radio frequency signal path and a negative feedback loop;

the radio frequency signal path includes: a first NMOS transistor and asecond NMOS transistor;

a gate of the first NMOS transistor is configured as a radio frequencysignal input end, a drain of the first NMOS transistor is connected witha source of the second NMOS transistor, and a source of the first NMOStransistor is connected with a ground terminal; a drain of the secondNMOS transistor is configured as a radio frequency signal output end andis connected with a first voltage source;

the negative feedback loop includes: a third NMOS transistor, a fourthNMOS transistor and a differential amplifier;

a gate of the third NMOS transistor is connected with an output end ofthe differential amplifier, a source of the third NMOS transistor isconnected with the ground terminal, and a drain of the third NMOStransistor is connected with a source of the fourth NMOS transistor; agate of the fourth NMOS transistor is connected with a reverse input endof the differential amplifier and is connected with a second voltagesource, and a drain of the fourth NMOS transistor is connected with aforward input end of the differential amplifier and is connected with afirst bias current source;

the gate of the first NMOS transistor is connected with the output endof the differential amplifier; a gate of the second NMOS transistor isconnected with the second voltage source;

each of the second NMOS transistor and the fourth NMOS transistoroperates in a saturation region, so that power control of the first NMOStransistor is performed.

In the above solution, the value of width-length ratio of the third NMOStransistor and the first NMOS transistor is equal to the value ofwidth-length ratio of the fourth NMOS transistor and the second NMOStransistor.

In the above solution, the power control circuit further includes: afirst resistor;

the gate of the first NMOS transistor is connected with the output endof the differential amplifier via the first resistor.

In the above solution, the power control circuit further includes: asecond resistor; the gate of the second NMOS transistor is connectedwith the second voltage source via the second resistor.

In the above solution, the power control circuit further includes: aninductor; the drain of the second NMOS transistor is connected with thefirst voltage source via the inductor.

In the above solution, when drain voltage and gate voltage of the fourthNMOS transistor are equal, the fourth NMOS transistor operates in thesaturation region.

In the above solution, the power control circuit further includes: afifth NMOS transistor; the gate of the fourth NMOS transistor isconnected with the reverse input end of the differential amplifier viathe fifth NMOS transistor; gate and drain of the fifth NMOS transistorare short-connected; a source of the fifth NMOS transistor is connectedwith a first end of a second bias current source; a second end of thesecond bias current source is connected with the ground terminal.

In the above solution, threshold voltage of the fifth NMOS transistor isequal to threshold voltage of the fourth NMOS transistor; the fifth NMOStransistor operates in a weak inversion region.

In the above solution, when drain voltage of the fourth NMOS transistoris equal to gate voltage of the fourth NMOS transistor minus thresholdvoltage thereof, the fourth NMOS transistor operates in the saturationregion.

In the above solution, the gate of the fourth NMOS transistor isconnected with the drain of the fifth NMOS transistor; the source of thefifth NMOS transistor is connected with the reverse input end of thedifferential amplifier.

Various embodiments of the present disclosure provide a power controlcircuit, including: a radio frequency signal path and a negativefeedback loop; the radio frequency signal path includes: a first NMOStransistor and a second NMOS transistor; a gate of the first NMOStransistor is configured as a radio frequency signal input end, a drainof the first NMOS transistor is connected with a source of the secondNMOS transistor, and a source of the first NMOS transistor is connectedwith a ground terminal; a drain of that second NMOS transistor isconfigured as a radio frequency signal output end and is connected witha first voltage source; the negative feedback loop includes: a thirdNMOS transistor, a fourth NMOS transistor and a differential amplifier;a gate of the third NMOS transistor is connected with an output end ofthe differential amplifier, a source of the third NMOS transistor isconnected with the ground terminal, and a drain of the third NMOStransistor is connected with a source of the fourth NMOS transistor; agate of the fourth NMOS transistor is connected with a reverse input endof the differential amplifier and is connected with a second voltagesource, and a drain of the fourth NMOS transistor is connected with aforward input end of the differential amplifier and is connected with afirst bias current source; the gate of the first NMOS transistor isconnected with the output end of the differential amplifier; a gate ofthe second NMOS transistor is connected with the second voltage source;each of the second NMOS transistor and the fourth NMOS transistoroperates in a saturation region. As such, the radio frequency signalpath does not pass through the analog signal, the performance of thefirst NMOS transistor is not affected, while the control accuracy of theoutput power is improved.

The power control circuit can be, for example, part of a wirelesscommunication apparatus and system.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of the first composition of apower control circuit according to some embodiments;

FIG. 2 is a schematic structural diagram of the second composition of apower control circuit according to some embodiments;

FIG. 3 is a schematic structural diagram of the first composition of apower control circuit of an embodiment of the disclosure;

FIG. 4 is a schematic structural diagram of the second composition of apower control circuit of an embodiment of the disclosure;

FIG. 5 is a schematic circuit diagram of the first application of apower control circuit of an embodiment of the disclosure;

FIG. 6 is a schematic structural diagram of the third composition of apower control circuit of an embodiment of the disclosure; and

FIG. 7 is a schematic circuit diagram of the second application of apower control circuit of an embodiment of the disclosure.

DETAILED DESCRIPTION

In order to understand the characteristics and technical contents of theembodiments of the disclosure in more detail, the implementation of theembodiments of the disclosure will be described in detail below withreference to the appended figures, which are for reference only and arenot intended to limit the embodiments of the disclosure.

FIG. 1 is a schematic structural diagram of the first composition of apower control circuit according to some embodiments. As illustrated inFIG. 1, the drain of the transistor MN3 is connected with a currentsource IB, the drain and the gate of the transistor MN3 areshort-circuited; the drain of the transistor MN1 is connected with thesource of the transistor MN2, the gate of the transistor MN1 isconfigured as a radio frequency signal input end; the gate of thetransistor MN3 is connected with the gate of the transistor MN1, and aresistor R1 is connected in series there-between, the source of thetransistor MN3 and the source of the transistor MN1 are both connectedwith a ground terminal; the gate of the transistor MN2 is connected witha voltage source VG, and a resistor R2 is connected in seriesthere-between, the drain of the transistor MN2 is connected with avoltage source VCC, and an inductor L is connected in seriesthere-between, while the drain of the transistor MN2 is configured as aradio frequency signal output end. Based on the above circuitconnection, the channel modulation effect objectively exists, whichintroduces a large deviation when the bias current IB passing throughMN3 is mirrored to MN1, thus leading to a large deviation of saturationpower.

FIG. 2 is a schematic structural diagram of the second composition of apower control circuit according to some embodiments. As illustrated inFIG. 2, a differential amplifier is added on the basis of FIG. 1, andspecifically, the forward input end of the differential amplifier isconnected with the drain of the transistor MN3, the reverse input end ofthe differential amplifier is connected with the drain of the transistorMN1, the output end of the differential amplifier is connected with thegate of the transistor MN3 and one end of the resistor R1. Other partsare connected in the same way as described in FIG. 1. Among them, thetransistor MN1, the transistor MN3 and the differential amplifier form afeedback loop. By introducing a differential operational amplifier, thedrain voltages of the transistors MN1 and MN3 are equal, thuseliminating the effect of channel length modulation effect and improvingthe control accuracy of current. However, due to the presence of theradio frequency power amplification transistor MN1 in the feedback loop,a part of the radio frequency signal path will pass through the analogsignal, which will interfere with the radio frequency signal and reducethe performance of the radio frequency power amplifier.

When a radio frequency power amplifier is saturated, a power controlcircuit is required to control the output power of the radio frequencypower amplifier. There are generally two ways of power control, namelycurrent control and voltage control, respectively. Herein, the way ofcurrent control is to control the gate bias voltage of the amplificationtransistor of the power amplifier so as to control the bias current ofthe amplification transistor.

Based on the problem that the channel length modulation effect affectsand reduces the performance of the radio frequency amplifier in theexisting power control circuit, the embodiments of the disclosureprovide a power control circuit, FIG. 3 is a structural circuit diagramof a power control circuit of an embodiment of the disclosure, whichsolves the above two problems. As illustrated in FIG. 3, the circuitspecifically includes: a radio frequency signal path and a negativefeedback loop;

the radio frequency signal path includes: a first NMOS transistor MN1and a second NMOS transistor MN2;

a gate of the transistor MN1 is configured as a radio frequency signalinput end, a drain of the transistor MN1 is connected with a source ofthe transistor MN2, and a source of the transistor MN1 is connected witha ground terminal; a drain of the transistor MN2 is configured as aradio frequency signal output end and is connected with a first voltagesource VCC;

the negative feedback loop includes: a third NMOS transistor MN3, afourth NMOS transistor MN4 and a differential amplifier;

a gate of the transistor MN3 is connected with an output end of thedifferential amplifier, a source of the transistor MN3 is connected withthe ground terminal, and a drain of the transistor MN3 is connected witha source of the transistor MN4; a gate of the transistor MN4 isconnected with a reverse input end of the differential amplifier and isconnected with a second voltage source VG, and a drain of the transistorMN4 is connected with a forward input end of the differential amplifierand is connected with a first bias current source IB;

the gate of the transistor MN1 is connected with the gate of thetransistor MN3; a gate of the transistor MN2 is connected with thesecond voltage source VG;

each of the transistor MN2 and the transistor MN4 operates in asaturation region, so that power control of the transistor MN1 isperformed.

In some embodiments, the value of width-length ratio of the transistorMN3 and the transistor MN1 is equal to the value of width-length ratioof the transistor MN4 and the transistor MN2.

Specifically, in order to avoid a large deviation when the first biascurrent passing through the transistor MN3 is mirrored to the transistorMN1, the drain voltage of the transistor MN3 shall be equal to the drainvoltage of the transistor MN1. Therefore, for the above purpose, thetransistor MN4 is added to the existing power control circuit of FIG. 1,and the value of width-length ratio of the transistor MN3 and thetransistor MN1 is equal to the value of width-length ratio of thetransistor MN4 and the transistor MN2.

In some embodiments, when drain voltage and gate voltage of thetransistor MN4 are equal, the transistor MN4 operates in the saturationregion.

Specifically, the gate of the transistor MN4 is connected with thereverse input end of the differential amplifier, and the drain of thetransistor MN4 is connected with the forward input end of thedifferential amplifier, so that the gate voltage and drain voltage ofthe transistor MN4 are equal. Furthermore, the gate-source voltage ofthe transistor MN4 is equal to the drain-source voltage of thetransistor MN4, and since the condition for the transistor MN4 operatingin the saturation region is that the gate-source voltage of thetransistor MN4 minus the threshold voltage thereof is less than thedrain-source voltage of the transistor MN4, the transistor MN4 operatesin the saturation region.

Furthermore, it is known that the transistor MN2 operates in thesaturation region, and the transistor MN4 also operates in thesaturation region; the gate of the transistor MN2 and the gate of thetransistor MN4 are both connected with the second voltage source VG; thevalue of width-length ratio of the transistor MN3 and the transistor MN1is equal to the value of width-length ratio of the transistor MN4 andthe transistor MN2, and based on the above three conditions, it isconcluded that the source voltage of the transistor MN2 is equal to thesource voltage of the transistor MN4.

The source of the transistor MN4 is connected with the drain of thetransistor MN3, the drain of the transistor MN1 is connected with thesource of the transistor MN2, so that the source voltage of thetransistor MN4 is equal to the drain voltage of the transistor MN3, andthe source voltage of the transistor MN2 is equal to the drain voltageof the transistor MN1. Furthermore, the drain voltage of the transistorMN3 is equal to the drain voltage of the transistor MN1, thus there isno large deviation when the first bias current source IB passing throughthe transistor MN3 is mirrored to the transistor MN1, thereby improvingthe control accuracy of the bias current passing through the transistorMN1.

In view of the schematic structural diagram of the first composition ofa power control circuit in FIG. 3, the disclosure gives a specificcircuit diagram. FIG. 4 is a schematic structural diagram of the secondcomposition of a power control circuit of an embodiment of thedisclosure.

As illustrated in FIG. 4, the radio frequency signal path includes: atransistor MN1 and a transistor MN2; a gate of the transistor MN1 isconfigured as a radio frequency signal input end, a drain of thetransistor MN1 is connected with a source of the transistor MN2, and asource of the transistor MN1 is connected with a ground terminal; adrain of the transistor MN2 is configured as a radio frequency signaloutput end and is connected with a voltage source VCC; the negativefeedback loop includes: a transistor MN3, a transistor MN4 and adifferential amplifier; a gate of the transistor MN3 is connected withan output end of the differential amplifier, a source of the transistorMN3 is connected with a ground terminal, and a drain of the transistorMN3 is connected with a source of the transistor MN4; a gate of thetransistor MN4 is connected with a reverse input end of the differentialamplifier and is connected with a voltage source VG, and a drain of thetransistor MN4 is connected with a forward input end of the differentialamplifier and is connected with a bias current source IB; the gate ofthe transistor MN1 is connected with the gate of the transistor MN3; agate of the transistor MN2 is connected with the voltage source VG; eachof the transistor MN2 and the transistor MN4 operates in a saturationregion, so that power control of the transistor MN1 is performed.

In the above technical solution, the radio frequency signal path doesnot pass through the analog signal, that is, the analog signal does notinterfere with the radio frequency signal, and does not reduce theperformance of the radio frequency power amplifier.

Herein, the value of width-length ratio of the transistor MN3 and thetransistor MN1 is equal to the value of width-length ratio of thetransistor MN4 and the transistor MN2.

The first end of resistor R1 is connected with the output end of thedifferential amplifier, and the second end of the resistor R1 isconnected with the gate of the transistor MN1.

The first end of resistor R2 is connected with the voltage source VG andis connected with the reverse input end of the differential amplifier,the second end of the resistor R2 is connected with the gate of thetransistor MN2.

One end of inductor L is connected with the drain of the transistor MN2and the other end of the inductor L is connected with the voltage sourceVCC.

The gate of the transistor MN4 is connected with the reverse input endof the differential amplifier, and the drain of the transistor MN4 isconnected with the forward input end of the differential amplifier, sothat the gate voltage and drain voltage of the transistor MN4 are equal.Furthermore, the gate-source voltage of the transistor MN4 is equal tothe drain-source voltage of the transistor MN4, and since the conditionfor the transistor MN4 operating in the saturation region is that thegate-source voltage of the transistor MN4 minus the threshold voltagethereof is less than the drain-source voltage of the transistor MN4, thetransistor MN4 operates in the saturation region.

Furthermore, it is known that the transistor MN2 operates in thesaturation region, and the transistor MN4 also operates in thesaturation region; the gate of the transistor MN2 and the gate of thetransistor MN4 are both connected with the voltage source VG; the valueof width-length ratio of the transistor MN3 and the transistor MN1 isequal to the value of width-length ratio of the transistor MN4 and thetransistor MN2, and based on the above three conditions, it is concludedthat the source voltage of the transistor MN2 is equal to the sourcevoltage of the transistor MN4.

The source of the transistor MN4 is connected with the drain of thetransistor MN3, the drain of the transistor MN1 is connected with thesource of the transistor MN2, so that the source voltage of thetransistor MN4 is equal to the drain voltage of the transistor MN3, andthe source voltage of the transistor MN2 is equal to the drain voltageof the transistor MN1. Furthermore, the drain voltage of the transistorMN3 is equal to the drain voltage of the transistor MN1, thus there isno large deviation when the bias current source IB1 passing through thetransistor MN3 is mirrored to the transistor MN1, thereby improving thecontrol accuracy of the bias current passing through the transistor MN1.

Various embodiments of the present disclosure provide a power controlcircuit, including: a radio frequency signal path and a negativefeedback loop; the radio frequency signal path includes: a first NMOStransistor and a second NMOS transistor; a gate of the first NMOStransistor is configured as a radio frequency signal input end, a drainof the first NMOS transistor is connected with a source of the secondNMOS transistor, and a source of the first NMOS transistor is connectedwith a ground terminal; a drain of that second NMOS transistor isconfigured as a radio frequency signal output end and is connected witha first voltage source; the negative feedback loop includes: a thirdNMOS transistor, a fourth NMOS transistor and a differential amplifier;a gate of the third NMOS transistor is connected with an output end ofthe differential amplifier, a source of the third NMOS transistor isconnected with the ground terminal, and a drain of the third NMOStransistor is connected with a source of the fourth NMOS transistor; agate of the fourth NMOS transistor is connected with a reverse input endof the differential amplifier and is connected with a second voltagesource, and a drain of the fourth NMOS transistor is connected with aforward input end of the differential amplifier and is connected with afirst bias current source; the gate of the first NMOS transistor isconnected with the output end of the differential amplifier; a gate ofthe second NMOS transistor is connected with the second voltage source;each of the second NMOS transistor and the fourth NMOS transistoroperates in a saturation region. As such, the radio frequency signalpath does not pass through the analog signal, the performance of thefirst NMOS transistor is not affected, while the control accuracy of theoutput power is improved.

FIG. 5 is a schematic circuit diagram of the first application of apower control circuit of an embodiment of the disclosure. As illustratedin FIG. 5, the differential amplifier circuit in the left dashed box isthe specific circuit diagram of the differential amplifier of the powercontrol circuit in FIG. 4.

Herein, the differential amplifier circuit includes: a bias currentsource IB3, a transistor MN8, a transistor MN7, a transistor MN6, atransistor MP1 and a transistor MP2; drain and gate of the transistorMN8 are short-circuited, and the drain of the transistor MN8 isconnected with the bias current source IB3; a drain of the transistorMN7 is connected with a drain of the transistor MP1; a drain of thetransistor MN6 is connected with a drain of the transistor MP2; thesources of the transistors MN8, MN7 and MN6 are all connected with aground terminal, the gate of the transistor MN8 is connected with a gateof the transistor MN7, the gate of the transistor MN7 is connected witha gate of the transistor MN6; the drain and gate of the transistor MP1are short-circuited, the gate of the transistor MP1 is connected with agate of the transistor MP2. Herein, the value of width-length ratio ofthe transistor MN7 and the transistor MN6 is equal to the value ofwidth-length ratio of the transistor MP1 and the transistor MP2.Furthermore, it may be concluded that the gate-source voltage of thetransistor MP1 is equal to the gate-source voltage of the transistorMP2.

Other parts of the power control circuit include: a bias current sourceIB1, a voltage source VG, a voltage source VCC, a transistor MN4, atransistor MN3, a transistor MN2, a transistor MN1, a resistor R1, aresistor R2, an inductor L, a radio frequency signal input end RFIN anda radio frequency signal output end RFOUT; herein, a gate of thetransistor MN4 is connected with the voltage source VG, a drain of thetransistor MN4 is connected with the bias current source IB1, and asource of the transistor MN4 is connected with a drain of the transistorMN3; a source of the transistor MN3 is connected with the groundterminal; a gate of the transistor MN1 is connected with the radiofrequency signal input end RFIN, a source of the transistor MN1 isconnected with the ground terminal, a drain of the transistor MN1 isconnected with a source of the transistor MN2; a drain of the transistorMN2 is connected with the radio frequency signal output end RFOUT, theradio frequency signal output end RFOUT is connected with one end of theinductor L, and the other end of the inductor L is connected with thevoltage source VCC; a gate of the transistor MN2 is connected with thegate of the transistor MN4 via the resistor R2; the gate of thetransistor MN1 is connected with a gate of the transistor MN3 via theresistor R1.

The source of the transistor MP2 is connected with the drain of thetransistor MN4, the source of the transistor MP1 is connected with thevoltage source VG, and the gate of the transistor MN3 is connected withthe drains of the transistor MN6 and the transistor MP2. The transistorMP2 of the operational amplifier circuit, the transistors MN3 and MN4 ofthe power amplifier circuit form a negative feedback loop.

Since the gate-source voltage of the transistor MP1 is equal to thegate-source voltage of the transistor MP2, and the gate of thetransistor MP1 is connected with the gate of the transistor MP2, thegate voltage of the transistor MP2 is equal to the voltage source VGminus the gate-source voltage of the transistor MP1, that is, the sourcevoltage of the transistor MP2 is equal to VG, that is, the drain voltageof the transistor MN4 is equal to VG, and the transistor MN4 operates ina saturation region.

The transistor MN2 also operates in the saturation region, and the gateof the transistor MN4 and the gate of the transistor MN2 are bothconnected with the voltage source VG, so that the source voltage of thetransistor MN2 is equal to the source voltage of the transistor MN4;since the source of the transistor MN4 is connected with the drain ofthe transistor MN3, and the drain of the transistor MN1 is connectedwith the source of the transistor MN2, the drain voltage of thetransistor MN3 is equal to the drain voltage of the transistor MN1, andthere is no large deviation when the bias current source IB1 passingthrough the transistor MN3 is mirrored to the transistor MN1, therebyimproving the control accuracy of the bias current of the transistorMN1.

In view of the schematic structural diagram of the first composition ofa power control circuit in FIG. 3, the disclosure gives another specificcircuit diagram, FIG. 6 is a schematic structural diagram of the thirdcomposition of a power control circuit of an embodiment of thedisclosure. That is, a transistor MN5 and a bias current source IB2 areadded on the basis of FIG. 3. Specifically, the connection of thecircuit of FIG. 6 is described as follows:

the power control circuit includes: a radio frequency signal path and anegative feedback loop; the radio frequency signal path includes: atransistor MN1, a transistor MN2 and a voltage source VCC; a gate of thetransistor MN1 is configured as a radio frequency signal input end, adrain of the transistor MN1 is connected with a source of the transistorMN2, and a source of the transistor MN1 is connected with a groundterminal; a drain of the transistor MN2 is configured as a radiofrequency signal output end and is connected with the voltage sourceVCC; the negative feedback loop includes: a transistor MN3, a transistorMN4 and a differential amplifier; a gate of the transistor MN3 isconnected with an output end of the differential amplifier, a source ofthe transistor MN3 is connected with the ground terminal, and a drain ofthe transistor MN3 is connected with a source of the transistor MN4; adrain of the transistor MN4 is connected with a forward input end of thedifferential amplifier and is connected with a bias current source IB1;a gate of the transistor MN4 is connected with a voltage source VG; thepower control circuit further includes: a transistor MN5 and a biascurrent source IB2; the gate of the transistor MN4 is connected with areverse input end of the differential amplifier via the transistor MN5,specifically, the gate of the transistor MN4 is connected with a drainof the transistor MN5; a source of the transistor MN5 is connected withthe reverse input end of the differential amplifier; the drain and gateof the transistor MN5 are short-circuited, the source of the transistorMN5 is connected with one end of the bias current source IB2; the otherend of the bias current source IB2 is connected with the groundterminal; the gate of the transistor MN1 is connected with the gate ofthe transistor MN3; a gate of the transistor MN2 is connected with thevoltage source VG; each of the transistor MN2 and the transistor MN4operates in a saturation region, so that power control of the transistorMN1 is performed.

In the above technical solution, the radio frequency signal path doesnot pass through the analog signal, that is, the analog signal does notinterfere with the radio frequency signal, and does not reduce theperformance of the radio frequency power amplifier.

In some embodiments, the value of width-length ratio of the third NMOStransistor and the first NMOS transistor is equal to the value ofwidth-length ratio of the fourth NMOS transistor and the second NMOStransistor.

In some embodiments, the power control circuit further includes: a firstresistor; the gate of the first NMOS transistor is connected with theoutput end of the differential amplifier via the first resistor.

Specifically, one end of resistor R1 is connected with the output end ofthe differential amplifier, and the other end of the resistor R1 isconnected with the gate of the transistor MN1.

In some embodiments, the power control circuit further includes: asecond resistor; the gate of the second NMOS transistor is connectedwith the second voltage source via the second resistor.

Specifically, one end of resistor R2 is connected with the voltagesource VG and is also connected with the reverse input end of thedifferential amplifier, the other end of the resistor R2 is connectedwith the gate of the transistor MN2.

In some embodiments, the power control circuit further includes: aninductor; the drain of the second NMOS transistor is connected with thefirst voltage source via the inductor.

Specifically, one end of inductor L is connected with the drain of thetransistor MN2 and the other end of the inductor L is connected with thevoltage source VCC.

In some embodiments, threshold voltage of the fifth NMOS transistor isequal to threshold voltage of the fourth NMOS transistor; the fifth NMOStransistor operates in a weak inversion region.

Specifically, the transistor MN5 operates in the weak inversion region,so that the gate-source voltage of the transistor MN5 is equal to thethreshold voltage thereof, herein, the condition for an NMOS transistoroperating in a weak inversion region is that the gate-source voltagethereof is equal to the threshold voltage thereof; since the gate of thetransistor MN5 is connected with the gate of the transistor MN4, and thegate of the transistor MN4 is connected with the voltage source VG, thesource voltage of the transistor MN5 is equal to the voltage source VGminus the threshold voltage of the transistor MN5.

Since the drain of the transistor MN4 is connected with the forwardinput end of the differential amplifier and the source of the transistorMN5 is connected with the inverse input end of the differentialamplifier, the drain voltage of the transistor MN4 is equal to thesource voltage of the transistor MN5. Furthermore, the drain-sourcevoltage of the transistor MN4 is equal to the gate-source voltage of thetransistor MN4 minus the threshold voltage thereof, and the transistorMN4 operates in the saturation region.

Furthermore, it is known that the transistor MN2 operates in thesaturation region, and the transistor MN4 also operates in thesaturation region; and the gate of the transistor MN2 and the gate ofthe transistor MN4 are both connected with the voltage source VG; basedon the above two conditions, it is concluded that the source voltage ofthe transistor MN2 is equal to the source voltage of the transistor MN4.

The source of the transistor MN4 is connected with the drain of thetransistor MN3, the drain of the transistor MN1 is connected with thesource of the transistor MN2, so that the source voltage of thetransistor MN4 is equal to the drain voltage of the transistor MN3, andthe source voltage of the transistor MN2 is equal to the drain voltageof the transistor MN1. Furthermore, the drain voltage of the transistorMN3 is equal to the drain voltage of the transistor MN1, thus there isno large deviation when the bias current source IB1 passing through thetransistor MN3 is mirrored to the transistor MN1, thereby improving thecontrol accuracy of the bias current passing through the transistor MN1.

The disclosure discloses a power control circuit, including: a radiofrequency signal path and a negative feedback loop; the radio frequencysignal path includes: a first NMOS transistor and a second NMOStransistor; a gate of the first NMOS transistor is configured as a radiofrequency signal input end, a drain of the first NMOS transistor isconnected with a source of the second NMOS transistor, and a source ofthe first NMOS transistor is connected with a ground terminal; a drainof the second NMOS transistor is configured as a radio frequency signaloutput end and is connected with a first voltage source; the negativefeedback loop includes: a third NMOS transistor, a fourth NMOStransistor and a differential amplifier; a gate of the third NMOStransistor is connected with an output end of the differentialamplifier, a source of the third NMOS transistor is connected with theground terminal, and a drain of the third NMOS transistor is connectedwith a source of the fourth NMOS transistor; a gate of the fourth NMOStransistor is connected with a reverse input end of the differentialamplifier and is connected with a second voltage source, and a drain ofthe fourth NMOS transistor is connected with a forward input end of thedifferential amplifier and is connected with a first bias currentsource; the gate of the first NMOS transistor is connected with theoutput end of the differential amplifier; a gate of the second NMOStransistor is connected with a second voltage source; each of the secondNMOS transistor and the fourth NMOS transistor operates in a saturationregion. As such, the radio frequency signal path does not pass throughthe analog signal, the performance of the first NMOS transistor is notaffected, while the control accuracy of the output power is improved.

FIG. 7 is a schematic circuit diagram of the second application of apower control circuit of an embodiment of the disclosure. As illustratedin FIG. 7, the differential amplifier circuit in the left dashed box isthe specific circuit diagram of the differential amplifier of the powercontrol circuit in FIG. 6. Herein, the source of the transistor MN5 isconnected with the source of the transistor MP1, so that the biascurrent source IB2 in FIG. 6 may be omitted.

Herein, the differential amplifier circuit includes: a bias currentsource IB3, a transistor MN8 , a transistor MN7, a transistor MN6, atransistor MN5, a transistor MP1 and a transistor MP2; drain and gate ofthe transistor MN8 are short-circuited, and the drain of the transistorMN8 is connected with the bias current source IB3; a drain of thetransistor MN7 is connected with a drain of the transistor MP1; a drainof the transistor MN6 is connected with a drain of the transistor MP2;the sources of the transistors MN8, MN7 and MN6 are all connected with aground terminal, the gate of the transistor MN8 is connected with a gateof the transistor MN7, the gate of the transistor MN7 is connected witha gate of the transistor MN6; gate and drain of the transistor MN5 areshort-circuited, a source of the transistor MN5 is connected with asource of the transistor MP1; the drain and gate of the transistor MP1are short-circuited, the gate of the transistor MP1 is connected with agate of the transistor MP2. Herein, the value of width-length ratio ofthe transistor MN7 and the transistor MN6 is equal to the value ofwidth-length ratio of the transistor MP1 and the transistor MP2,Furthermore, it may be concluded that the gate-source voltage of thetransistor MP1 is equal to the gate-source voltage of the transistorMP2; the transistor MN5 operates in a weak inversion region, thus thegate-source voltage of the transistor MN5 is equal to the thresholdvoltage thereof

Other parts of the power control circuit include: a bias current sourceIB1, a voltage source VG, a voltage source VCC, a transistor MN4, atransistor MN3, a transistor MN2, a transistor MN1, a resistor R1, aresistor R2, an inductor L, a radio frequency signal input end RFIN anda radio frequency signal output end RFOUT; herein, a gate of thetransistor MN4 is connected with the voltage source VG, a drain of thetransistor MN4 is connected with the bias current source IB1, and asource of the transistor MN4 is connected with a drain of the transistorMN3; a source of the transistor MN3 is connected with the groundterminal; a gate of the transistor MN1 is connected with the radiofrequency signal input end RFIN, a source of the transistor MN1 isconnected with the ground terminal, a drain of the transistor MN1 isconnected with a source of the transistor MN2; a drain of the transistorMN2 is connected with the radio frequency signal output end RFOUT, theradio frequency signal output end RFOUT is connected with one end of theinductor L, and the other end of the inductor L is connected with thevoltage source VCC; a gate of the transistor MN2 is connected with thegate of the transistor MN4 via the resistor R2; the gate of thetransistor MN1 is connected with a gate of the transistor MN3 via theresistor R1.

The source of the transistor MP2 is connected with the drain of thetransistor MN4, the source of the transistor MN5 is connected with thevoltage source VG, and the gate of the transistor MN3 is connected withthe drains of the transistor MN6 and the transistor MP2.

Since the gate-source voltage of the transistor MP1 is equal to thegate-source voltage of the transistor MP2, the gate of the transistorMP1 is connected with the gate of the transistor MP2, the source of thetransistor MP1 is connected with the source of the transistor MN5, thesource of the transistor MP2 is connected with the drain of thetransistor MN4, and the threshold voltage of the transistor MN5 is equalto the threshold voltage of the transistor MN4, the drain voltage of thetransistor MN4 is equal to VG minus the threshold voltage thereof, thatis, the transistor MN4 operates in a saturation region.

The transistor MN2 also operates in the saturation region, and the gateof the transistor MN4 and the gate of the transistor MN2 are bothconnected with the voltage source VG, so that the source voltage of thetransistor MN2 is equal to the source voltage of the transistor MN4;since the source of the transistor MN4 is connected with the drain ofthe transistor MN3, and the drain of the transistor MN1 is connectedwith the source of the transistor MN2, the drain voltage of thetransistor MN3 is equal to the drain voltage of the transistor MN1, andthere is no large deviation when the bias current source IB1 passingthrough the transistor MN3 is mirrored to the transistor MN1, therebyimproving the control accuracy of the bias current of the transistorMN1.

The above descriptions are only specific embodiments of the disclosure,but the protection scope of the disclosure is not limited to thereto,and any technicians familiar with this technical field may easilyconceive of changes or substitutions within the technical scopedisclosed in the disclosure, which should be covered within theprotection scope of the disclosure. Therefore, the protection scope ofthe disclosure shall be based on the protection scope of the claims.

The disclosure discloses a power control circuit, including: a radiofrequency signal path and a negative feedback loop; the radio frequencysignal path includes: a first NMOS transistor and a second NMOStransistor; a gate of the first NMOS transistor is configured as a radiofrequency signal input end, a drain of the first NMOS transistor isconnected with a source of the second NMOS transistor, and a source ofthe first NMOS transistor is connected with a ground terminal; a drainof the second NMOS transistor is configured as a radio frequency signaloutput end and is connected with a first voltage source; the negativefeedback loop includes: a third NMOS transistor, a fourth NMOStransistor and a differential amplifier; a gate of the third NMOStransistor is connected with an output end of the differentialamplifier, a source of the third NMOS transistor is connected with theground terminal, and a drain of the third NMOS transistor is connectedwith a source of the fourth NMOS transistor; a gate of the fourth NMOStransistor is connected with a reverse input end of the differentialamplifier and is connected with a second voltage source, and a drain ofthe fourth NMOS transistor is connected with a forward input end of thedifferential amplifier and is connected with a first bias currentsource; the gate of the first NMOS transistor is connected with theoutput end of the differential amplifier; a gate of the second NMOStransistor is connected with the second voltage source; each of thesecond NMOS transistor and the fourth NMOS transistor operates in asaturation region. As such, the radio frequency signal path does notpass through the analog signal, the performance of the first NMOStransistor is not affected, while the control accuracy of the outputpower is improved.

In several embodiments provided in the disclosure, it should beunderstood that the disclosed device and method may be implemented inother ways. The above-mentioned device embodiments are merelyillustrative, for example, the division of the units is only a divisionbased on logical functions, and there may be other divisions in actualimplementations, e.g., multiple units or components may be combined, ormay be integrated in another system, or some features may be ignored, ormay not be performed. In addition, the coupling, or direct coupling, orcommunication connection between the components illustrated or discussedmay be indirect coupling or communication connection through someinterfaces, devices or units, which may be electrical, mechanical orotherwise.

The above-mentioned units illustrated as separate components may be ormay not be physically separated, and the components illustrated as unitsmay be or may not be physical units, i.e., they may be located in oneplace or distributed to multiple network units; some or all of the unitsmay be selected according to actual needs to achieve the purpose of thesolutions of the embodiments.

In addition, each functional unit in each of the embodiments of thedisclosure may be all integrated in a processing unit, or each unit maybe separately present as a single unit, or two or more units may beintegrated in a single unit; the above integrated units may be realizedeither in the form of hardware or in the form of hardware together withsoftware functional units.

Those ordinarily skilled in the art may understand that all or a part ofthe steps for realizing the above-mentioned embodiments of the methodmay be realized by hardware related to program instructions, and theabove-mentioned program may be stored in a computer readable storagemedium, and when the program is executed, the steps including theabove-mentioned embodiments of the method are executed; and theabove-mentioned storage medium includes various medium that may storeprogram codes, such as mobile storage devices, Read-Only Memory (ROM),Random Access Memory (RAM), magnetic disks or optical disks, etc.

Or, the above integrated unit in the disclosure may also be stored in acomputer-readable storage medium, when it is implemented as a softwarefunction module and sold or used as an individual product. Based on suchunderstanding, the technical solutions of the embodiments of thedisclosure substantially or the part contributing to the related art maybe embodied in the form of a software product, and the computer softwareproduct is stored in a storage medium and includes several instructionsto allow a computer device (which may be a personal computer, a server,or a network equipment, etc.) to execute all or part of the methoddescribed in each of the embodiments of the disclosure. And theaforementioned storage medium includes various medium that may storeprogram codes, such as mobile storage devices, ROM, RAM, magnetic disksor optical disks etc.

While this specification contains many specific implementation details,these should not be construed as limitations on the scope of any claims,but rather as descriptions of features specific to particularimplementations. Certain features that are described in thisspecification in the context of separate implementations can also beimplemented in combination in a single implementation. Conversely,various features that are described in the context of a singleimplementation can also be implemented in multiple implementationsseparately or in any suitable subcombination.

Moreover, although features can be described above as acting in certaincombinations and even initially claimed as such, one or more featuresfrom a claimed combination can in some cases be excised from thecombination, and the claimed combination can be directed to asubcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particularorder, this should not be understood as requiring that such operationsbe performed in the particular order shown or in sequential order, orthat all illustrated operations be performed, to achieve desirableresults. In certain circumstances, multitasking and parallel processingcan be advantageous. Moreover, the separation of various systemcomponents in the implementations described above should not beunderstood as requiring such separation in all implementations, and itshould be understood that the described program components and systemscan generally be integrated together in a single software product orpackaged into multiple software products.

As such, particular implementations of the subject matter have beendescribed. Other implementations are within the scope of the followingclaims. In some cases, the actions recited in the claims can beperformed in a different order and still achieve desirable results. Inaddition, the processes depicted in the accompanying figures do notnecessarily require the particular order shown, or sequential order, toachieve desirable results. In certain implementations, multitasking orparallel processing can be utilized.

The above description includes part of embodiments of the presentdisclosure, and not limits the present disclosure. Any modifications,equivalent substitutions, improvements, etc., within the spirit andprinciples of the present disclosure, are included in the scope ofprotection of the present disclosure.

It is apparent that those of ordinary skill in the art can make variousmodifications and variations to the embodiments of the disclosurewithout departing from the spirit and scope of the disclosure. Thus, itis intended that the present disclosure cover the modifications and themodifications.

Various embodiments in this specification have been described in aprogressive manner, where descriptions of some embodiments focus on thedifferences from other embodiments, and same or similar parts among thedifferent embodiments are sometimes described together in only oneembodiment.

It should also be noted that in the present disclosure, relational termssuch as first and second, etc., are only used to distinguish one entityor operation from another entity or operation, and do not necessarilyrequire or imply these entities having such an order or sequence. Itdoes not necessarily require or imply that any such actual relationshipor order exists between these entities or operations.

Moreover, the terms “include,” “including,” or any other variationsthereof are intended to cover a non-exclusive inclusion within aprocess, method, article, or apparatus that comprises a list of elementsincluding not only those elements but also those that are not explicitlylisted, or other elements that are inherent to such processes, methods,goods, or equipment.

In the case of no more limitation, the element defined by the sentence“includes a . . . ” does not exclude the existence of another identicalelement in the process, the method, or the device including the element.

Specific examples are used herein to describe the principles andimplementations of some embodiments. The description is only used tohelp convey understanding of the possible methods and concepts.Meanwhile, those of ordinary skill in the art can change the specificmanners of implementation and application thereof without departing fromthe spirit of the disclosure. The contents of this specificationtherefore should not be construed as limiting the disclosure.

For example, in the description of the present disclosure, the terms“some embodiments,” or “example,” and the like may indicate a specificfeature described in connection with the embodiment or example, astructure, a material or feature included in at least one embodiment orexample. In the present disclosure, the schematic representation of theabove terms is not necessarily directed to the same embodiment orexample.

Moreover, the particular features, structures, materials, orcharacteristics described can be combined in a suitable manner in anyone or more embodiments or examples. In addition, various embodiments orexamples described in the specification, as well as features of variousembodiments or examples, can be combined and reorganized.

In the descriptions, with respect to circuit(s), unit(s), device(s),component(s), etc., in some occurrences singular forms are used, and insome other occurrences plural forms are used in the descriptions ofvarious embodiments. It should be noted; however, the single or pluralforms are not limiting but rather are for illustrative purposes. Unlessit is expressly stated that a single unit, device, or component etc. isemployed, or it is expressly stated that a plurality of units, devicesor components, etc. are employed, the circuit(s), unit(s), device(s),component(s), etc. can be singular, or plural.

Based on various embodiments of the present disclosure, the disclosedapparatuses, devices, and methods can be implemented in other manners.For example, the abovementioned devices can employ various methods ofuse or implementation as disclosed herein.

In the present disclosure, the terms “installed,” “connected,”“coupled,” “fixed” and the like shall be understood broadly, and may beeither a fixed connection or a detachable connection, or integrated,unless otherwise explicitly defined. These terms can refer to mechanicalor electrical connections, or both. Such connections can be directconnections or indirect connections through an intermediate medium.These terms can also refer to the internal connections or theinteractions between elements. The specific meanings of the above termsin the present disclosure can be understood by those of ordinary skillin the art on a case-by-case basis.

Dividing the device into different “regions,” “units,” “components” or“layers,” etc. merely reflect various logical functions according tosome embodiments, and actual implementations can have other divisions of“regions,” “units,” “components” or “layers,” etc. realizing similarfunctions as described above, or without divisions. For example,multiple regions, units, or layers, etc. can be combined or can beintegrated into another system. In addition, some features can beomitted, and some steps in the methods can be skipped.

Those of ordinary skill in the art will appreciate that the units,components, regions, or layers, etc. in the devices provided by variousembodiments described above can be provided in the one or more devicesdescribed above. They can also be located in one or multiple devicesthat is (are) different from the example embodiments described above orillustrated in the accompanying drawings. For example, the units,regions, or layers, etc. in various embodiments described above can beintegrated into one module or divided into several sub-modules.

The various device components, modules, units, blocks, or portions mayhave modular configurations, or are composed of discrete components, butnonetheless can be referred to as “modules” in general. In other words,the “components,” “modules,” “blocks,” “portions,” or “units” referredto herein may or may not be in modular forms, and these phrases may beinterchangeably used.

Moreover, the terms “first” and “second” are used for descriptivepurposes only and are not to be construed as indicating or implying arelative importance or implicitly indicating the number of technicalfeatures indicated. Thus, elements referred to as “first” and “second”may include one or more of the features either explicitly or implicitly.In the description of the present disclosure, “a plurality” indicatestwo or more unless specifically defined otherwise.

The order of the various embodiments described above are only for thepurpose of illustration, and do not represent preference of embodiments.

Although specific embodiments have been described above in detail, thedescription is merely for purposes of illustration. It should beappreciated, therefore, that many aspects described above are notintended as required or essential elements unless explicitly statedotherwise.

Various modifications of, and equivalent acts corresponding to thedisclosed aspects of the exemplary embodiments can be made in additionto those described above by a person of ordinary skill in the art havingthe benefit of the present disclosure without departing from the spiritand scope of the disclosure contemplated by this disclosure and asdefined in the following claims. As such, the scope of this disclosureis to be accorded the broadest reasonable interpretation so as toencompass such modifications and equivalent structures.

What is claimed is:
 1. A power control circuit, comprising: a radiofrequency signal path; and a negative feedback loop; wherein the radiofrequency signal path comprises: a first NMOS transistor and a secondNMOS transistor; a gate of the first NMOS transistor is configured as aradio frequency signal input end, a drain of the first NMOS transistoris connected with a source of the second NMOS transistor, and a sourceof the first NMOS transistor is connected with a ground terminal; adrain of the second NMOS transistor is configured as a radio frequencysignal output end and is connected with a first voltage source; thenegative feedback loop comprises: a third NMOS transistor, a fourth NMOStransistor and a differential amplifier; a gate of the third NMOStransistor is connected with an output end of the differentialamplifier, a source of the third NMOS transistor is connected with theground terminal, and a drain of the third NMOS transistor is connectedwith a source of the fourth NMOS transistor; a gate of the fourth NMOStransistor is connected with a reverse input end of the differentialamplifier and is connected with a second voltage source, and a drain ofthe fourth NMOS transistor is connected with a forward input end of thedifferential amplifier and is connected with a first bias currentsource; the gate of the first NMOS transistor is connected with theoutput end of the differential amplifier; a gate of the second NMOStransistor is connected with the second voltage source; each of thesecond NMOS transistor and the fourth NMOS transistor operates in asaturation region, so that power control of the first NMOS transistor isperformed.
 2. The power control circuit of claim 1, wherein the value ofwidth-length ratio of the third NMOS transistor and the first NMOStransistor is equal to the value of width-length ratio of the fourthNMOS transistor and the second NMOS transistor.
 3. The power controlcircuit of claim 1, further comprising: a first resistor; wherein thegate of the first NMOS transistor is connected with the output end ofthe differential amplifier via the first resistor.
 4. The power controlcircuit of claim 3, further comprising: a second resistor; wherein thegate of the second NMOS transistor is connected with the second voltagesource via the second resistor.
 5. The power control circuit of claim 4,further comprising: an inductor; wherein the drain of the second NMOStransistor is connected with the first voltage source via the inductor.6. The power control circuit of claim 1, wherein when drain voltage andgate voltage of the fourth NMOS transistor are equal, the fourth NMOStransistor operates in the saturation region.
 7. The power controlcircuit of claim 5, further comprising: a fifth NMOS transistor; whereinthe gate of the fourth NMOS transistor is connected with the reverseinput end of the differential amplifier via the fifth NMOS transistor;the gate of the fourth NMOS transistor is connected with a drain of thefifth NMOS transistor; a source of the fifth NMOS transistor isconnected with the reverse input end of the differential amplifier; thedrain and gate of the fifth NMOS transistor are short-circuited; thesource of the fifth NMOS transistor is connected with a first end of asecond bias current source; a second end of the second bias currentsource is connected with the ground terminal.
 8. The power controlcircuit of claim 7, wherein a threshold voltage of the fifth NMOStransistor is equal to threshold voltage of the fourth NMOS transistor;the fifth NMOS transistor operates in a weak inversion region.
 9. Thepower control circuit of claim 7, wherein when a drain voltage of thefourth NMOS transistor is equal to gate voltage of the fourth NMOStransistor minus threshold voltage thereof, the fourth NMOS transistoroperates in the saturation region.
 10. A wireless communicationapparatus comprising the power control circuit of claim 1, wherein theradio frequency signal path does not pass through analog signals,without affecting performance of the first NMOS transistor, whilecontrol accuracy of the power control circuit is improved.
 11. Theapparatus of claim 10, wherein the value of width-length ratio of thethird NMOS transistor and the first NMOS transistor is equal to thevalue of width-length ratio of the fourth NMOS transistor and the secondNMOS transistor.
 12. The apparatus of claim 10, further comprising: afirst resistor; wherein the gate of the first NMOS transistor isconnected with the output end of the differential amplifier via thefirst resistor.
 13. The apparatus of claim 12, further comprising: asecond resistor; wherein the gate of the second NMOS transistor isconnected with the second voltage source via the second resistor. 14.The apparatus of claim 13, further comprising: an inductor; wherein thedrain of the second NMOS transistor is connected with the first voltagesource via the inductor.
 15. The apparatus of claim 10, wherein whendrain voltage and gate voltage of the fourth NMOS transistor are equal,the fourth NMOS transistor operates in the saturation region.
 16. Theapparatus of claim 14, further comprising: a fifth NMOS transistor;wherein the gate of the fourth NMOS transistor is connected with thereverse input end of the differential amplifier via the fifth NMOStransistor; the gate of the fourth NMOS transistor is connected with adrain of the fifth NMOS transistor; a source of the fifth NMOStransistor is connected with the reverse input end of the differentialamplifier; the drain and gate of the fifth NMOS transistor areshort-circuited; the source of the fifth NMOS transistor is connectedwith a first end of a second bias current source; a second end of thesecond bias current source is connected with the ground terminal. 17.The apparatus of claim 16, wherein a threshold voltage of the fifth NMOStransistor is equal to threshold voltage of the fourth NMOS transistor;the fifth NMOS transistor operates in a weak inversion region.
 18. Theapparatus of claim 16, wherein when a drain voltage of the fourth NMOStransistor is equal to gate voltage of the fourth NMOS transistor minusthreshold voltage thereof, the fourth NMOS transistor operates in thesaturation region.